1. Field of the Invention
The present invention relates to a method of fabricating a memory device. More particularly, the present invention relates to a method of fabricating a one-time programmable read only memory (OTPROM).
2. Description of the Related Art
With the power of microprocessors continues to expand, the amount of computation in given software programs increases exponentially. As a result, there is an urgent demand for cheap and high storage capacity memories from semiconductor manufacturers. According to the difference in read/write capability, memories can be roughly classified into read only memory (ROM) and random access memory (RAM).
Read only memory is a type of non-volatile data storage device that can retain stored data even when the power is cut off. Hence, most standard electrical products are equipped with some read only memory for holding a normal operation.
According to data storage format, read only memory (ROM) can be further sub-divided into mask ROM, one-time programmable ROM (OTPROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) and so on. Since data can be programmed into a one-time programmable ROM outside the factory according to the particular environment the memory is supposed to be working in, one-time programmable ROM is more convenient to work with than the mask ROM.
In the other hand, a single semiconductor chip are usually divided into a memory cell area and a peripheral circuit area, wherein the memory cell area includes at least a memory cell, while the peripheral circuit area includes at least a logic device. For cases in which both memory cells and logic devices are used on the single semiconductor chip, low sheet resistances are needed for the logic devices, while higher sheet resistances are needed for the memory cells. Therefore, salicide layers are formed on the logic devices needing low sheet resistances to fabricate the higher performing devices, while other regions of the semiconductor chip, not requiring the lower sheet resistances, have been masked from the salicide process.
The masking of the higher sheet resistance devices, during the process used to form salicide layers on the requiring low sheet resistance regions, is usually accomplished using a silicon oxide layer. The silicon oxide layer is formed by a plasma-enhanced chemical vapor deposition (PECVD), and its thickness is about 500 Å. In addition, because the silicon oxide layer cannot react with metal in the following salicide step, the silicon oxide layer is also named as a salicide blocking layer (SAB).
Furthermore, in the current trend of driver IC, in order to simply the entire process and reduce wafer cost, the single poly OTPROM, which has only one gate over a substrate, with standard logic process is the best candidate. However, in the standard logic process flow, the SAB layer will induce poor OTP retention issue because it cannot block mobile ion intrusion and cause charge gain and charge loss.